A multi-core system having a configuration depicted in FIG. 8 has been known. In this multi-core system, a multiple processor cores #0_1 and #1_2 are connected to bus networks 3 and 4, to which multiple buses 5 and 6 are connected. To each of the buses 5 and 6, one or more peripheral devices A7, B8, C9, and D10 are connected. A task #1_11 under execution at the processor core #0_1 and a task #2_12 under execution at the processor core #1_2 may access, during the same period, the peripheral device A7 (or peripheral device B8) and the peripheral device C9 (or peripheral device D10) connected separately to the bus 5 and the bus 6, respectively. In this case, contention at a bus does not occur.
In another case, the task #1_11 and the task #2_12 may access, during the same period, the peripheral device A7 and the peripheral device B8 (or peripheral device C9 and peripheral device D10) connected to the same bus 5 (or bus 6). In this case, contention at the bus occurs and consequently, a bus arbiter arbitrates the contention. As a result of the arbitration, one access is permitted first and following the completion of this access, the other access is permitted.
A load balancing method is known where statistical information indicating a busy state of a bus is attached to a job executed by a processor core and scheduling for alleviating the busy state of the bus is performed based on this statistical information. A bus control method is known that when a bus is being used, a processor executes a different task while waiting to acquire a right to use the bus and when the right to use the bus is released, the processor is caused to execute an interrupt process to use the bus. A system is known that switches processes between different processors during execution of processes to dynamically perform optimal assignment.
For examples of such conventional technologies, refer to Japanese Laid-Open Patent Publication Nos. H10-240698, 114-354044, and H6-214959.
According to the conventional arbitration technique using a bus arbiter, however, permission for the other access is not given until the access permitted first is completed. The processor core waiting for permission for the other access, therefore, suspends (stalls) task execution. As a result, the time required for completing execution of the two tasks causing access contention at the bus increases, which leads to a problem in that the performance of the multi-core system drops.